Freescale Semiconductor MPC5604B - Page 25

MPC5604B/C Microcontroller Reference Manual, Rev. 8
14 Freescale Semiconductor
27.4.2 Flash memory module sectorization .............................................................................642
27.4.3 TestFlash block .............................................................................................................643
27.4.4 Shadow sector ...............................................................................................................645
27.4.5 User mode operation .....................................................................................................645
27.4.6 Reset .............................................................................................................................646
27.4.7 Power-down mode ........................................................................................................647
27.4.8 Low power mode ..........................................................................................................647
27.5 Register description .......................................................................................................................648
27.5.1 CFlash register description ...........................................................................................649
27.5.2 DFlash register description ...........................................................................................680
27.6 Programming considerations .........................................................................................................703
27.6.1 Modify operation ..........................................................................................................703
27.6.2 Double word program ...................................................................................................704
27.6.3 Sector erase ...................................................................................................................706
27.7 Platform flash memory controller .................................................................................................714
27.7.1 Introduction ..................................................................................................................714
27.7.2 Memory map and register description ..........................................................................717
27.8 Functional description ...................................................................................................................726
27.8.1 Access protections ........................................................................................................727
27.8.2 Read cycles – Buffer miss ............................................................................................727
27.8.3 Read cycles – Buffer hit ...............................................................................................727
27.8.4 Write cycles ..................................................................................................................727
27.8.5 Error termination ..........................................................................................................727
27.8.6 Access pipelining ..........................................................................................................728
27.8.7 Flash error response operation ......................................................................................728
27.8.8 Bank0 page read buffers and prefetch operation ..........................................................728
27.8.9 Bank1 Temporary Holding Register .............................................................................730
27.8.10 Read-while-write functionality .....................................................................................731
27.8.11 Wait-state emulation .....................................................................................................732
Chapter 28
Static RAM (SRAM)
28.1 Introduction ...................................................................................................................................735
28.2 Low power configuration ..............................................................................................................735
28.3 Register memory map ...................................................................................................................735
28.4 SRAM ECC mechanism ................................................................................................................735
28.4.1 Access timing ...............................................................................................................736
28.4.2 Reset effects on SRAM accesses ..................................................................................737
28.5 Functional description ...................................................................................................................737
28.6 Initialization and application information .....................................................................................737
Chapter 29
Register Protection
29.1 Introduction ...................................................................................................................................741
29.2 Features .........................................................................................................................................741