Freescale Semiconductor MPC5604B - 3. Hardware mode INTC

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 13
Chapter 25
Analog-to-Digital Converter (ADC)
25.1 Overview .......................................................................................................................................591
25.1.1 Device-specific features ...............................................................................................591
25.1.2 Device-specific implementation ...................................................................................592
25.2 Introduction ...................................................................................................................................592
25.3 Functional description ...................................................................................................................593
25.3.1 Analog channel conversion ..........................................................................................593
25.3.2 Analog clock generator and conversion timings ..........................................................597
25.3.3 ADC sampling and conversion timing .........................................................................597
25.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................599
25.3.5 Presampling ..................................................................................................................600
25.3.6 Programmable analog watchdog ..................................................................................601
25.3.7 Interrupts .......................................................................................................................602
25.3.8 External decode signals delay ......................................................................................603
25.3.9 Power-down mode ........................................................................................................603
25.3.10 Auto-clock-off mode ....................................................................................................603
25.4 Register descriptions .....................................................................................................................604
25.4.1 Introduction ..................................................................................................................604
25.4.2 Control logic registers ..................................................................................................607
25.4.3 Interrupt registers ..........................................................................................................611
25.4.4 Threshold registers .......................................................................................................618
25.4.5 Presampling registers ....................................................................................................619
25.4.6 Conversion timing registers CTR[0..2] ........................................................................622
25.4.7 Mask registers ...............................................................................................................622
25.4.8 Delay registers ..............................................................................................................627
25.4.9 Data registers ................................................................................................................628
Chapter 26
Cross Triggering Unit (CTU)
26.1 Introduction ...................................................................................................................................631
26.2 Main features .................................................................................................................................631
26.3 Block diagram ...............................................................................................................................631
26.4 Memory map and register descriptions .........................................................................................631
26.4.1 Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................632
26.5 Functional description ...................................................................................................................633
26.5.1 Channel value ...............................................................................................................635
Chapter 27
Flash Memory
27.1 Introduction ...................................................................................................................................639
27.2 Main features .................................................................................................................................640
27.3 Block diagram ...............................................................................................................................640
27.4 Functional description ...................................................................................................................641
27.4.1 Module structure ...........................................................................................................641