Freescale Semiconductor MPC5604B - Page 3

MPC5604BRMAD, Rev. 2
Freescale Semiconductor2
1 Addendum List for Revision 8.1
2 Addendum List for Revision 8
Table 1. MPC5604BCRM Rev 8.1 Addenda
Location Description
Chapter 27, “Flash Memory”
page 644
Add a note below Table 27-4, “CFlash TestFlash Structure”.
NOTE
Unique Device ID – Memory location. This device now includes a 128-bit Unique
Identification number (UID) which is programmed during device fabrication.
Start – Stop Address Size (Bytes) Content:
• 0x00403C10 0x00403C17 8 UID 1
• 0x00403C18 0x00403C1F 8 UID 2
Table 2. MPC5604BCRM Rev 8 Addenda
Location Description
Chapter 4, Signal description,
page 60
In Table 4-3, Functional port pin descriptions, row PH[9], change the pin numbers for
MPC560xB 64 LQFP and MPC560xC 64 LQFP from “—” to 60.
In row PH[10], change the pin numbers for MPC560xB 64 LQFP and MPC560xC 64 LQFP
from “—” to 53.
Chapter 6, Clock Description,
page 113
Add Note: to Section 6.8.4.1, Crystal clock monitor:
Note: Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is
greater than (FIRC / 2
RCDIV
)+0.5MHz.
Add Note: to Section 6.8.4.2, FMPLL clock monitor:
Note: Functional FMPLL monitoring can only be guaranteed when the FMPLL frequency is
greater than (FIRC / 4) + 0.5 MHz.
Chapter 9, Reset Generation
Module (MC_RGM), page
209
Replace Section 9.4.7, Boot Mode Capturing, with the following:
The MC_RGM samples PA[9:8] whenever RESET is asserted until five FIRC (16 MHz internal
RC oscillator) clock cycles before its deassertion edge. The result of the sampling is used at
the beginning of reset PHASE3 for boot mode selection and is retained after RESET has been
deasserted for subsequent boots after reset sequences during which RESET is not asserted.
Note: In order to ensure that the boot mode is correctly captured, the application needs to
apply the valid boot mode value the entire time that RESET is asserted.
RESET can be asserted as a consequence of the internal reset generation. This will force
re-sampling of the boot mode pins. (See Table 9-12 for details.)
Chapter 13, Real Time Clock /
Autonomous Periodic
Interrupt (RTC/API), page
262
In Table 13-3 (RTCC field descriptions), update Note in RTCC[APIVAL] field description:
Note: API functionality starts only when APIVAL is nonzero. The first API interrupt takes two
more cycles because of synchronization of APIVAL to the RTC clock, and APIVAL + 1 cycles
for subsequent occurrences. After that, interrupts are periodic in nature. Because of
synchronization issues, the minimum supported value of APIVAL is 4.