MPC5604BRMAD, Rev. 2
Freescale Semiconductor 3
Chapter 21, LINFlex, p. 412 Insert the following section:
21.8.2.1.6 Overrun
Once the message buffer is full, the next valid message reception leads to an
overrun and a message is lost. The hardware sets the BOF bit in the LINSR to
signal the overrun condition. Which message is lost depends on the
configuration of the RX message buffer:
• If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last
message stored in the buffer is overwritten by the new incoming
message. In this case the latest message is always available to the
application.
• If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most
recent message is discarded and the previous message is available in the
buffer.
Chapter 22, FlexCAN,
throughout chapter
Remove references throughout the chapter to “low-cost MCUs.”
Chapter 22, FlexCAN, page
429
Add this Note in the RTR field description of Table 22-4 (Message Buffer Structure field
description):
Note: Do not configure the last Message Buffer to be the RTR frame.
Chapter 22, FlexCAN, page
461
In Section 22.4.9.4, Protocol timing, update the Note following Figure 22-16 (CAN engine
clocking scheme) to read: “This clock selection feature may not be available in all MCUs. A
particular MCU may not have a PLL, in which case it would have only the oscillator clock, or
it may use only the PLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit
in the CTRL Register has no effect on the module operation.”
Chapter 22, FlexCAN, page
462
Update the table title of Table 22-20 from “CAN Standard Compliant Bit Time Segment Settings”
to “Bosch CAN 2.0B standard compliant bit time segment settings.”
Chapter 22, FlexCAN, page
463
In Section 22.4.9.4, Protocol timing, update the Note following Table 22-20 to read: “Other
combinations of Time Segment 1 and Time Segment 2 can be valid. It is the user’s
responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit
time calculations, use an IPT (Information Processing Time) of 2, which is the value
implemented in the FlexCAN module.”
Chapter 25, Analog-to-Digital
Converter (ADC), page
In Section 28.3.5.2, Presampling channel enable signals, in Table 28-7, Presampling voltage
selection based on PREVALx fields, in the 01 row, change the “Presampling voltage” field to:
V1 = V
DD_HV_ADC0
or V
DD_HV_ADC1
.
Chapter 25, Analog-to-Digital
Converter (ADC), page 597
In Section 25.3.2, Analog clock generator and conversion timings, remove the paragraph:
The direct clock should basically be used only in low power mode when the device is using
only the 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock
(an 8 MHz clock is not fast enough). In all other cases, the ADC should use the clock divided
by two internally.
Table 2. MPC5604BCRM Rev 8 Addenda
Location Description
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