Freescale Semiconductor MPC5604B - Page 332

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 321
M3PE Bus master 3 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M3SM Bus master 3 supervisor mode access control
This field defines the access controls for bus master 3 when operating in supervisor mode. The M3SM
field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M3UM for user mode
M3UM Bus master 3 user mode access control
This field defines the access controls for bus master 3 when operating in user mode. The M3UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
M2PE Bus master 2 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M2SM Bus master 2 supervisor mode access control
This field defines the access controls for bus master 2 when operating in supervisor mode. The M2SM
field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M2UM for user mode
M2UM Bus master 2 user mode access control
This field defines the access controls for bus master 2 when operating in user mode. The M2UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
M1PE Bus master 1 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M1SM Bus master 1 supervisor mode access control
This 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. The
M1SM field is defined as:
0b00 r, w, x = read, write and execute allowed
0b01 r, –, x = read and execute allowed, but no write
0b10 r, w, – = read and write allowed, but no execute
0b11 Same access controls as that defined by M1UM for user mode
M1UM Bus master 1 user mode access control
This 3-bit field defines the access controls for bus master 1 when operating in user mode. The M1UM
field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the
bit allows the given access type to occur; if cleared, an attempted access of that mode may be
terminated with an access error (if not allowed by any other descriptor) and the access not performed.
Table 18-9. MPU_RGDAACn field descriptions (continued)
Field Description