Freescale Semiconductor MPC5604B - Page 331

MPC5604B/C Microcontroller Reference Manual, Rev. 8
320 Freescale Semiconductor
Since the MPU_RGDAACn register is simply another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 18-9 are identical to those presented in Table 18-7.
Offset: 0x800 + (4*n) (MPU_RGDAACn) Access: Read/write
0123456789101112131415
R
M7RE
M7WE
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
M3PE
M3SM M3UM
M2PE
M2SM[1]
W
Reset––––––––––––––––
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
M2SM[0]
M2UM
M1PE
M1SM M1UM
M0PE
M0SM M0UM
W
Reset––––––––––––––––
Figure 18-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Table 18-9. MPU_RGDAACn field descriptions
Field Description
M7RE Bus master 7 read enable.
If set, this flag allows bus master 7 to perform read operations. If cleared, any attempted read by bus
master 7 terminates with an access error and the read is not performed.
M7WE Bus master 7 write enable
If set, this flag allows bus master 7 to perform write operations. If cleared, any attempted write by bus
master 7 terminates with an access error and the write is not performed.
M6RE Bus master 6 read enable
If set, this flag allows bus master 6 to perform read operations. If cleared, any attempted read by bus
master 6 terminates with an access error and the read is not performed.
M6WE Bus master 6 write enable
If set, this flag allows bus master 6 to perform write operations. If cleared, any attempted write by bus
master 6 terminates with an access error and the write is not performed.
M5RE Bus master 5 read enable
If set, this flag allows bus master 5 to perform read operations. If cleared, any attempted read by bus
master 5 terminates with an access error and the read is not performed.
M5WE Bus master 5 write enable
If set, this flag allows bus master 5 to perform write operations. If cleared, any attempted write by bus
master 5 terminates with an access error and the write is not performed.
M4RE Bus master 4 read enable
If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus
master 4 terminates with an access error and the read is not performed.
M4WE Bus master 4 write enable
If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus
master 4 terminates with an access error and the write is not performed.