MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 365
20.3.5 I
2
C Bus Status Register (IBSR)
RSTA Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is
the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong
time, if the bus is owned by another master, will result in loss of arbitration.
1 Generate repeat start cycle
0 No effect
DMAEN DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I
2
C module
requires data to be read or written to the data register. No Transfer Done interrupts will be generated
when this bit is set, however an interrupt will be generated if the loss of arbitration or addressed as slave
conditions occur. The DMA mode is only valid when the I
2
C module is configured as a Master and the
DMA transfer still requires CPU intervention at the start and the end of each frame of data. See the DMA
Application Information section for more details.
1 Enable the DMA TX/RX request signals
0 Disable the DMA TX/RX request signals
Offset 0x3 Access: Read-write
76543210
R TCF IAAS IBB IBAL 0 SRW IBIF RXAK
W w1c w1c
Reset10000000
Figure 20-7. I
2
C Bus Status Register (IBSR)
Table 20-9. IBSR Field Descriptions
Field Description
TCF Transfer complete. While one byte of data is being transferred, this bit is cleared. It is set by the falling
edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a
transfer to the I
2
C module or from the I
2
C module.
1 Transfer complete
0 Transfer in progress
IAAS Addressed as a slave. When its own specific address (I-Bus Address Register) is matched with the
calling address, this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to
check the SRW bit and set its Tx/Rx
mode accordingly. Writing to the I-Bus Control Register clears this
bit.
1 Addressed as a slave
0 Not addressed
IBB Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a
STOP signal is detected, IBB is cleared and the bus enters idle state.
1Bus is busy
0 Bus is Idle
Table 20-8. IBCR field descriptions (continued)
Field Description
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