MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 373
as a data transfer complete flag as the flag timing is dependent on a number of factors including the I
2
C
bus frequency. This bit may not conclusively provide an indication of a transfer complete situation. It is
recommended that transfer complete situations are detected using the IBIF flag
Software may service the I
2
C I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when a “Transfer Complete” interrupt occurs at the end of the address cycle, the master will
always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated
by R/W bit sent with slave calling address, then the Tx/Rx bit at Master side should be toggled at this stage.
If Master does not receive an ACK from Slave, then transmission must be re-initiated or terminated.
In slave mode, IAAS bit will get set in IBSR if Slave address (IBAD) matches the Master calling address.
This is an indication that Master-Slave data communication can now start. During address cycles
(IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer
and the Tx/Rx bit is programmed accordingly. For slave mode data cycles (IAAS=0), the SRW bit is not
valid. The Tx/Rx bit in the control register should be read to determine the direction of the current transfer.
20.5.1.4 Transmit/receive sequence
Follow this sequence in case of Master Transmit(Address/Data):
1. Clear IBSR[IBIF].
2. Write data in Data Register (IBDR).
3. IBSR[TCF] bit will get cleared when transfer is in progress.
4. IBSR[TCF] bit will get set when transfer is complete.
5. Wait for IBSR[IBIF] to get set, then read IBSR register to determine its source:
— TCF = 1 i.e. transfer is complete.
— No Acknowledge condition (RXAK = 1) is found.
— IBB = 0 i.e. Bus has transitioned from Busy to Idle state.
— If IBB = 1, ignore check of Arbitration Loss (IBAL = 1).
— Ignore Address Detect (IAAS = 1) for Master mode (valid only for Slave mode).
6. f) Check RXAK in IBSR for an acknowledge from slave.
Follow this sequence in case of Slave Receive(Address/Data):
1. Clear IBSR[IBIF].
2. IBSR[TCF] will get cleared when transfer is in progress for address transfer.
3. IBSR[TCF] will get set when transfer is complete.
4. Wait for IBSR[IBIF] to get set. Then read IBSR register to determine its source:
— Address Detect has occurred (IAAS = 1) - determination of Slave mode.
5. Clear IBIF.
6. Wait until IBSR[TCF] bit gets cleared (that is, "Transfer under Progress" condition is reached for
data transfer).
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