MPC5604B/C Microcontroller Reference Manual, Rev. 8
374 Freescale Semiconductor
7. Wait until IBSR[TCF] bit gets cleared(proof that Transfer Completes from "Transfer under
Progress" state).
8. Wait until IBSR[IBIF] bit gets set. To find its source, check if:
— TCF = 1 i.e. reception is complete
— IBSR[IBB] = 0, that is, bus has transitioned from Busy to Idle state
— Ignore Arbitration Loss (IBAL = 1) for IBB = 1
— Ignore No Acknowledge condition (RXAK = 1) for receiver
9. Read the Data Register (IBDR) to determine data received from Master.
Sequence followed in case of Slave Transmit (Steps 1–4 of Slave Receive for Address Detect, followed by
1–6 of Master Transmit for Data Transmit).
Sequence followed in case of Master Receive (Steps 1–6 of Master Transmit for Address dispatch,
followed by 5–8 of Slave Receive for Data Receive).
20.5.1.5 Generation of STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply
generate a STOP signal after all the data has been transmitted. The following is an example showing how
a stop condition is generated by a master transmitter.
if (tx_count == 0) or// check to see if all data bytes have been transmitted
(bit 0, IBSR == 1) {// or if no ACK generated
clear bit 5, IBCR// generate stop condition
}
else {
IBDR = data_to_transmit// write byte of data to DATA register
tx_count --// decrement counter
}// return from interrupt
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK)
before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must first be
generated. The following is an example showing how a STOP signal is generated by a master receiver.
rx_count --// decrease the rx counter
if (rx_count ==1)// 2nd last byte to be read ?
bit 3, IBCR = 1// disable ACK
if (rx_count == 0)// last byte to be read ?
bit 5, IBCR = 0// generate stop signal
else
data_received = IBDR// read RX data and store
20.5.1.6 Generation of repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can generate another
START signal followed by another slave address without first generating a STOP signal. A program
example is as shown.
bit 2, IBCR = 1// generate another start ( restart)
IBDR == calling_address// transmit the calling address
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