MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 397
21.7.1.8 LIN output compare register (LINOCR)
TOCE Timeout counter enable
0 Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare
event.
1 Timeout counter enable. OCF bit is set if an output compare event occurs.
TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in
LIN timeout mode, then hardware takes control of TOCE bit.
CNT Counter Value
This field indicates the LIN timeout counter value.
Offset: 0x001C Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OC2
1
OC1
1
W
Reset1111111111111111
1
If LINTCSR[LTOM] = 1, this field is read-only.
Figure 21-13. LIN output compare register (LINOCR)
Table 21-13. LINOCR field descriptions
Field Description
OC2 Output compare 2 value
These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR.
OC1 Output compare 1 value
These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR.
Table 21-12. LINTCSR field descriptions (continued)
Field Description
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