MPC5604B/C Microcontroller Reference Manual, Rev. 8
408 Freescale Semiconductor
21.7.1.21 Identifier filter control register (IFCR2n +1)
NOTE
This register can be written in Initialization mode only.
Offsets: 0x0050–0x0088 (8 registers) Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 000
DFL DIR CCS
00 ID
W w1c
Reset0000000000000000
Figure 21-26. Identifier filter control register (IFCR2n +1)
Table 21-29. IFCR2n + 1 field descriptions
Field Description
DFL Data Field Length
This field defines the number of data bytes in the response part of the frame.
DFL = Number of data bytes – 1.
DIR Direction
This bit controls the direction of the data field.
0 LINFlex receives the data and copies them in the BDRL and BDRM registers.
1 LINFlex transmits the data from the BDRL and BDRM registers.
CCS Classic Checksum
This bit controls the type of checksum applied on the current message.
0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN
specification 2.0 and higher.
1 Classic Checksum covering Data field only. This is compatible with LIN specification 1.3 and
earlier.
ID Identifier
Identifier part of the identifier field without the identifier parity
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