MPC5604B/C Microcontroller Reference Manual, Rev. 8
434 Freescale Semiconductor
Offset: 0x0000 Access: Read/write
0123456789101112131415
R
MDIS
FRZ FEN
HALT
NOT_RDY
0
SOFT_RST
FRZ_ACK
SUPV
0
WRN_EN
LPM_ACK
00
SRX_DIS
BCC
W
Reset Note
1
1
Reset value of this bit is different on various platforms. Consult the specific MCU documentation to determine its
value.
101100
Note
2
2
Different on various platforms, but it is always the opposite of the MDIS reset value.
100
Note
3
3
Different on various platforms, but it is always the same as the MDIS reset value.
0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0
LPRIO_EN
AEN
00
IDAM
00
MAXMB
W
Reset
0000000000001111
Figure 22-5. Module Configuration Register (MCR)
Table 22-8. MCR field descriptions
Field Description
MDIS Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the only
bit in MCR not affected by soft reset. See Section 22.4.10.2, “Module Disable Mode for more
information.
1 = Disable the FlexCAN module
0 = Enable the FlexCAN module
FRZ Freeze Enable
The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR is set or when Debug
Mode is requested at MCU level. When FRZ is asserted, FlexCAN is enabled to enter Freeze Mode.
Negation of this bit field causes FlexCAN to exit from Freeze Mode.
1 = Enabled to enter Freeze Mode
0 = Not enabled to enter Freeze Mode
FEN FIFO Enable
This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot
be used for normal reception and transmission because the corresponding memory region
(0x80–0xFF) is used by the FIFO engine. See Section 22.3.3, “Rx FIFO structure and
Section 22.4.8, “Rx FIFO for more information. This bit must be written in Freeze mode only.
1 = FIFO enabled
0 = FIFO not enabled
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