MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 435
HALT Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after
initializing the Message Buffers and Control Register. No reception or transmission is performed by
FlexCAN before this bit is cleared. While in Freeze Mode, the CPU has write access to the Error
Counter Register, that is otherwise read-only. Freeze Mode cannot be entered while FlexCAN is in
the low power mode. See Section 22.4.10.1, “Freeze Mode for more information.
1 = Enters Freeze Mode if the FRZ bit is asserted.
0 = No Freeze Mode request.
NOT_RDY FlexCAN Not Ready
This read-only bit indicates that FlexCAN is either in Disable Mode or Freeze Mode. It is negated
once FlexCAN has exited these modes.
1 = FlexCAN module is either in Disable Mode or Freeze Mode
0 = FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
SOFT_RST Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory
mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR,
IMASK1, IMASK2, IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN
bus are not affected by soft reset. The following registers are unaffected:
•CTRL
• RXIMR0–RXIMR63
• RXGMASK, RX14MASK, RX15MASK
• all Message Buffers
The SOFT_RST bit can be asserted directly by the CPU when it writes to the MCR, but it is also
asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and has
to follow a request/acknowledge procedure across clock domains, it may take some time to fully
propagate its effect. The SOFT_RST bit remains asserted while reset is pending, and is
automatically negated when reset completes. Therefore, software can poll this bit to know when the
soft reset has completed.
Soft reset cannot be applied while clocks are shut down in the low power mode. The module should
be first removed from low power mode, and then soft reset can be applied.
1 = Resets the registers marked as “affected by soft reset” in Table 22-2
0 = No reset request
FRZ_ACK Freeze Mode Acknowledge
This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler is stopped. The Freeze
Mode request cannot be granted until current transmission or reception processes have finished.
Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually entered
Freeze Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN
prescaler is running again. If Freeze Mode is requested while FlexCAN is in the low power mode,
then the FRZ_ACK bit will only be set when the low power mode is exited. See Section 22.4.10.1,
“Freeze Mode for more information.
1 = FlexCAN in Freeze Mode, prescaler stopped
0 = FlexCAN not in Freeze Mode, prescaler running
SUPV Supervisor Mode
This bit configures some of the FlexCAN registers to be either in Supervisor or Unrestricted memory
space. The registers affected by this bit are marked as S/U in the Access Type column of Ta bl e 2 2-2.
Reset value of this bit is ‘1’, so the affected registers start with Supervisor access restrictions.This
bit should be written in Freeze mode only.
1 = Affected registers are in Supervisor memory space. Any access without supervisor permission
behaves as though the access was done to an unimplemented register location
0 = Affected registers are in Unrestricted memory space
Table 22-8. MCR field descriptions (continued)
Field Description
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