MPC5604B/C Microcontroller Reference Manual, Rev. 8
444 Freescale Semiconductor
such bits and then wraps around while incrementing the TX_ERR_COUNTER. When
TX_ERR_COUNTER reaches the value of 128, the FLT_CONF field in the Error and Status
Register is updated to be ‘Error Active’ and both error counters are reset to zero. At any instance
of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter
resets itself to zero without affecting the TX_ERR_COUNTER value.
• If during system start-up, only one node is operating, then its TX_ERR_COUNTER increases in
each message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR
bit in the Error and Status Register). After the transition to ‘Error Passive’ state, the
TX_ERR_COUNTER does not increment anymore by acknowledge errors. Therefore the device
never goes to the ‘Bus Off’ state.
• If the RX_ERR_COUNTER increases to a value greater than 127, it is not incremented further,
even if more errors are detected while being a receiver. At the next successful message reception,
the counter is set to a value between 119 and 127 to resume to ‘Error Active’ state.
22.3.4.8 Error and Status Register (ESR)
This register reflects various error conditions, some general status of the device and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16–23. Bits 22–28 are status bits.
Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, WAK_INT and
ERR_INT, that are interrupt flags that can be cleared by writing ‘1’ to them (writing ‘0’ has no effect). See
Section 22.4.11, “Interrupts for more details.
Offset: 0x001C Access: Read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RX_ERR_COUNTER TX_ERR_COUNTER
W
Reset0000000000000000
Figure 22-9. Error Counter Register (ECR)
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