MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 445
Offset: 0x0020 Access: Read/write
0123456789101112131415
R00000000000000
TWRN_INT
RWRN_INT
W
Reset00000000000000 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BIT1_ ERR
BIT0_ ERR
ACK_ ERR
CRC_ERR
FRM_ERR
STF_ERR
TX_WRN
RX_WRN
IDLE
TXRX
FLT_CONF 0
BOFF_INT
ERR_ INT
0
W
Reset00000000000000 0 0
= Unimplemented or Reserved
Figure 22-10. Error and Status Register (ESR)
Table 22-12. ESR field descriptions
Field Description
TWRN_INT Tx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition
from ‘0’ to ‘1’, meaning that the Tx error counter reached 96. If the corresponding mask bit in the
Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing it to ‘1’. Writing ‘0’ has no effect.
1 = The Tx error counter transition from < 96 to 96
0 = No such occurrence
RWRN_INT Rx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition
from ‘0’ to ‘1’, meaning that the Rx error counters reached 96. If the corresponding mask bit in the
Control Register (RWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing it to ‘1’. Writing ‘0’ has no effect.
1 = The Rx error counter transition from < 96 to 96
0 = No such occurrence
BIT1_ERR Bit1 Error
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
message.
1 = At least one bit sent as recessive is received as dominant
0 = No such occurrence
Note: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node
sending a passive error flag that detects dominant bits.
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