MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 479
fields in the DSPIx_CTAR0 and DSPIx_CTAR1 registers are used to set the slave transfer attributes. See
the individual bit descriptions for details on which bits are used in slave modes.
When the DSPI is configured as an SPI master, the CTAS field in the command portion of the TX FIFO
entry selects which of the DSPIx_CTAR registers is used on a per-frame basis. When the DSPI is
configured as an SPI bus slave, the DSPIx_CTAR0 register is used.
.
Offsets: 0x0C–0x20 (6 registers) Access: Read/write
0123456789101112131415
R
DBR FMSZ
CPOL
CPHA
LSBFE
PCSSCK PASC PDT PBR
W
Reset0111100000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CSSCK ASC DT BR
W
Reset0000000000000000
Figure 23-5. DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn)
Table 23-5. DSPIx_CTARn field descriptions
Field Descriptions
DBR Double Baud Rate
The DBR bit doubles the effective baud rate of the Serial Communications Clock (SCK). This field is only
used in Master Mode. It effectively halves the Baud Rate division ratio supporting faster frequencies and
odd division ratios for the Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle
of the Serial Communications Clock (SCK) depends on the value in the Baud Rate Prescaler and the
Clock Phase bit as listed in Table 23-12. See the BR[0:3] field description for details on how to compute
the baud rate. If the overall baud rate is divide by two or divide by three of the system clock then neither
the Continuous SCK Enable or the Modified Timing Format Enable bits should be set.
0 The baud rate is computed normally with a 50/50 duty cycle
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler
FMSZ Frame Size
The FMSZ field selects the number of bits transferred per frame. The FMSZ field is used in Master Mode
and Slave Mode. Table 23-13 lists the frame size encodings.
CPOL Clock Polarity
The CPOL bit selects the inactive state of the Serial Communications Clock (SCK). This bit is used in
both Master and Slave Mode. For successful communication between serial devices, the devices must
have identical clock polarities. When the Continuous Selection Format is selected, switching between
clock polarities without stopping the DSPI can cause errors in the transfer due to the peripheral device
interpreting the switch of clock polarity as a valid clock edge.
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
To Next Page
Loading...
