MPC5604B/C Microcontroller Reference Manual, Rev. 8
504 Freescale Semiconductor
the idle state of the SCK_x. The clock phase bit selects if the data on SOUT_x is valid before or on the first
SCK_x edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPIx_CTAR0 (SPI slave mode) select the
polarity and phase of the serial clock. Even though the bus slave does not control the SCK signal, clock
polarity, clock phase and number of bits to transfer must be identical for the master device and the slave
device to ensure proper transmission.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified transfer format with CPHA = 0
• Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPIx_MCR selects between classic SPI
format and modified transfer format. The classic SPI formats are described in Section 23.6.5.1, Classic SPI
transfer format (CPHA = 0) and Section 23.6.5.2, Classic SPI transfer format (CPHA = 1). The modified
transfer formats are described in Section 23.6.5.3, Modified SPI transfer format (MTFE = 1, CPHA = 0)
and Section 23.6.5.4, Modified SPI transfer format (MTFE = 1, CPHA = 1).
In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames.
See Section 23.6.5.5, Continuous selection format for details.
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