Freescale Semiconductor MPC5604B - Page 521

MPC5604B/C Microcontroller Reference Manual, Rev. 8
510 Freescale Semiconductor
Figure 23-20 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0.
Figure 23-20. Example of non-continuous format (CPHA = 1, CONT = 0)
When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CS
signal remains asserted for the duration of the two transfers. The delay between transfers (t
DT
) is not
inserted between the transfers.
Figure 23-21 shows the timing diagram for two 4-bit transfers with CPHA = 1 and CONT = 1.
Figure 23-21. Example of continuous transfer (CPHA = 1, CONT = 1)
In Figure 23-21, the period length at the start of the next transfer is the sum of t
ASC
and t
CSC
; that is, it
does not include a half-clock period. The default settings for these provide a total of four system clocks.
In many situations, t
ASC
and t
CSC
must be increased if a full half-clock period is required.
Switching CTARs between frames while using continuous selection can cause errors in the transfer. The
CS signal must be negated before CTAR is switched.
SCK
(CPOL = 0)
CSx
t
ASC
SCK
(CPOL = 1)
Master SOUT
t
DT
t
CSC
t
CSC
= CS to SCK delay.
t
ASC
= After SCK delay.
t
DT
= Delay after transfer (minimum CS negation time).
Master SIN
t
CSC
SCK
(CPOL = 0)
CS
t
ASC
SCK
(CPOL = 1)
Master SOUT
t
CSC
t
CSC
t
CSC
= CS to SCK delay.
t
ASC
= After SCK delay.
Master SIN