Freescale Semiconductor MPC5604B - Page 596

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 585
24.5.4.6 Timer Flag Register (TFLG)
This register holds the PIT interrupt flags.
Offset: channel_base + 0x08 Access: Read/Write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000000000
TIE TEN
W
Reset0000000000000000
Figure 24-60. Timer Control Register (TCTRL)
Table 24-28. TCTRL field descriptions
Field Description
TIE Timer Interrupt Enable Bit
0 Interrupt requests from Timer x are disabled
1 Interrupt will be requested whenever TIF is set
When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt event.
To avoid this, the associated TIF flag must be cleared first.
TEN Timer Enable Bit
0 Timer will be disabled
1 Timer will be active
Offset: channel_base + 0x0C Access: Read/Write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000000TIF
W
w1c
Reset0000000000000000
Figure 24-61. Timer Flag Register (TFLG)