MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 707
6. Confirm MCR[PEG] = 1.
7. Write a logic 0 to the MCR[EHV] bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the MCR[ERS] bit to terminate the erase operation.
After setting MCR[ERS], one write, referred to as an interlock write, must be performed before
MCR[EHV] can be set to ‘1’. Data words written during erase sequence interlock writes are ignored.
The user may terminate the erase sequence by clearing ERS before setting EHV.
An erase operation may be aborted by clearing MCR[EHV] assuming MCR[DONE] is low, MCR[EHV]
is high and MCR[ESUS] is low.
An erase abort forces the module to step 8 of the erase sequence.
An aborted erase will result in MCR[PEG] being set low, indicating a failed operation. MCR[DONE] must
be checked to know when the aborting command has completed.
The block(s) being operated on before the abort contain indeterminate data. This may be recovered by
executing an erase on the affected blocks.
The user may not abort an erase sequence while in erase suspend.
Example 27-2. Erase of sectors B0F1 and B0F2
MCR = 0x00000004; /* Set ERS in MCR: Select Operation */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors to erase */
(0x000000) = 0xFFFFFFFF; /* Latch a flash memory Address with any data */
MCR = 0x00000005; /* Set EHV in MCR: Operation Start */
do /* Loop to wait for DONE=1 */
{ tmp = MCR; /* Read MCR */
} while ( !(tmp & 0x00000400) );
status = MCR & 0x00000200; /* Check PEG flag */
MCR = 0x00000004; /* Reset EHV in MCR: Operation End */
MCR = 0x00000000; /* Reset ERS in MCR: Deselect Operation */
27.6.3.1 Erase suspend/resume
The erase sequence may be suspended to allow read access to the flash memory core.
It is not possible to program or to erase during an erase suspend.
During erase suspend, all reads to blocks targeted for erase return indeterminate data.
An erase suspend can be initiated by changing the value of the MCR[ESUS] bit from 0 to 1. MCR[ESUS]
can be set to ‘1’ at any time when MCR[ERS] and MCR[EHV] are high and MCR[PGM] is low. A 0 to 1
transition of MCR[ESUS] causes the module to start the sequence which places it in erase suspend.
The user must wait until MCR[DONE] = 1 before the module is suspended and further actions are
attempted. MCR[DONE] will go high no more than t
ESUS
after MCR[ESUS] is set to ‘1’.
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