MPC5604B/C Microcontroller Reference Manual, Rev. 8
758 Freescale Semiconductor
30.5.2.2 SWT Interrupt Register (SWT_IR)
The SWT_IR contains the time-out interrupt flag.
HLK Hard Lock. This bit is only cleared at reset.
0 = SWT_CR, SWT_TO and SWT_WN are read/write registers if SLK=0
1 = SWT_CR, SWT_TO and SWT_WN are read only registers
SLK Soft Lock. This bit is cleared by writing the unlock sequence to the service register.
0 = SWT_CR, SWT_TO and SWT_WN are read/write registers if HLK=0
1 = SWT_CR, SWT_TO and SWT_WN are read only registers
CSL Clock Selection. Selects the SIRC oscillator clock that drives the internal timer.
CSL bit can be written.The status of the bit has no effect on counter clock selection on MPC5604B
device.
0 = System clock (Not applicable in MPC5604B)
1 = Oscillator clock
STP Stop Mode Control. Allows the watchdog timer to be stopped when the device enters STOP mode.
0 = SWT counter continues to run in STOP mode
1 = SWT counter is stopped in STOP mode
FRZ Debug Mode Control. Allows the watchdog timer to be stopped when the device enters debug mode.
0 = SWT counter continues to run in debug mode
1 = SWT counter is stopped in debug mode
WEN Watchdog Enabled.
0 = SWT is disabled
1 = SWT is enabled
Offset 0x0004 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000 0 00
W
Reset
0000000000000 0 00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 00000000000000
TIF
W
Reset
0000000000000 0 00
Figure 30-2. SWT Interrupt Register (SWT_IR)
Table 30-2. SWT_CR field descriptions
Field Description
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