MPC5604B/C Microcontroller Reference Manual, Rev. 8
770 Freescale Semiconductor
• Platform RAM ECC Syndrome Register (PRESR)
• Platform RAM ECC Master Number Register (PREMR)
• Platform RAM ECC Attributes Register (PREAT)
• Platform RAM ECC Data Register (PREDR)
The details on the ECC registers are provided in the subsequent sections.
31.4.2.7.1 ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches which
are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in
the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the ECSM captures specific information (memory address, attributes
and data, bus master number, etc.) which may be useful for subsequent failure analysis.
Offset: 0x43 Access: Read/write
01234567
R0 0
ER1BR EF1BR
00
ERNCR EFNCR
W
Reset:00000000
Figure 31-7. ECC Configuration (ECR) Register
Table 31-8. ECR field descriptions
Field Description
ER1BR Enable SRAM 1-bit Reporting
The occurrence of a single-bit SRAM correction generates a ECSM ECC interrupt request as
signalled by the assertion of ESR[R1BC]. The address, attributes and data are also captured in the
PREAR, PRESR, PREMR, PREAT and PREDR registers.
0 Reporting of single-bit SRAM corrections is disabled.
1 Reporting of single-bit SRAM corrections is enabled.
EF1BR Enable Flash 1-bit Reporting
The occurrence of a single-bit flash correction generates a ECSM ECC interrupt request as signalled
by the assertion of ESR[F1BC]. The address, attributes and data are also captured in the PFEAR,
PFEMR, PFEAT and PFEDR registers.
0 Reporting of single-bit flash corrections is disabled.
1 Reporting of single-bit flash corrections is enabled.
ERNCR Enable SRAM Non-Correctable Reporting
The occurrence of a non-correctable multi-bit SRAM error generates a ECSM ECC interrupt request
as signalled by the assertion of ESR[RNCE]. The faulting address, attributes and data are also
captured in the PREAR, PRESR, PREMR, PREAT and PREDR registers.
0 Reporting of non-correctable SRAM errors is disabled.
1 Reporting of non-correctable SRAM errors is enabled.
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