MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 905
Reset Generation
Module
Changed STANDBY0 to STANDBY.
Revised the chapter to reflect the fact that the RGM_DEAR and RGM_DERD registers are
always read-only.
In the “External Reset” section, changed “In this case, the external reset is forced low by
the product until the beginning of PHASE3” to “In this case, the external reset is asserted
until the end of PHASE3”.
Revised the RGM_FEAR[AR_CMU_OLR] field description.
Revised the RGM_FES[F_CORE] field description.
Changed “core reset” to “debug control core reset”.
Power Control Unit Changed HALT0 to HALT.
Changed STOP0 to STOP.
Changed STANDBY0 to STANDBY.
Voltage Regulators and
Power Supplies
In the “Register description” section, added information on where to find the VREG_CTL
base address.
Revised the “Register description” section to include the address offset and MC_PCU
mapping.
Wakeup Unit Changed WKUP to WKPU to match the official module abbreviation.
In the Overview section, replaced the wakeup vector mapping information with a table.
In the Overview section, changed the entries in “Interrupt vector 2” so that the footnote “Not
available in 100-pin LQFP” is associated only with WKPU[19].
In the “NMI management” section, changed “This register is a clear-by-write-1 register type,
preventing inadvertent overwriting of other flags in the same register.” to “The NIF and
NOVF fields in this register are cleared by writing a ‘1’ to them; this prevents inadvertent
overwriting of other flags in the register.”
In the “External interrupt management” section, changed “This register is a clear-by-write-1
register type, preventing inadvertent overwriting of other flags in the same register.” to
“The bits in the WISR[EIF] field are cleared by writing a ‘1’ to them; this prevents
inadvertent overwriting of other flags in the register.”
In the NSR, changed NIF to NIF0 and NOVF to NOVF0.
In the NCR, changed all field names to contain a trailing ‘0’ (example: NLOCK0).
In the “WKPU block diagram” figure, deleted single 0s.
In the “Memory map” section, changed “If supported and enabled by the SoC” to “If
SSCM_ERROR[RAE] is enabled”.
In the WIFER section, deleted “The number of wakeups ... 1 and 18”.
In the “WKPU memory map” table, added the module base address.
In the NCR[NWRE0] field description, added a note about the proper sequence for enabling
the NMI.
Real Time Clock /
Autonomous Periodic
Interrupt
Replaced ipg_clk with “system clock”.
Changed “32 kHz” to “32 KHz”.
Revised the RTCC[FRZEN] field description.
Added the following note to the RTCC[RTCVAL] field description: “RTCVAL = 0 does not
generate an interrupt.”.
In the “RTC functional description” section, deleted “The RTCC[RTCVAL] field may only be
updated when the RTCC[CNTEN] bit is cleared to disable the counter”.
In the “RTC/API register map” table, added the module base address.
CAN Sampler Deleted the duplicate register map.
In the “CAN sampler memory map” table, added the module base address.
e200z0h Core In the “e200z0h block diagram” figure, added a box around the core elements.
Table B-1. Changes between revisions 7 and 8 (continued)
Chapter Description
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