MPC5604B/C Microcontroller Reference Manual, Rev. 8
906 Freescale Semiconductor
Interrupt Controller Revised “INTC Priority Select Registers“ and “INTC Priority Select Register Address
Offsets“ table to show that “INTC_PSR208_210“ contains PRI208, PRI209, and PRI210
fields.
Revised the INTC_IACKR section to illustrate the register’s dependence on
INTC_MCR[VTES] more clearly.
In the INTC_EOIR register figure, added “See text” to the W row.
In the “Interrupt vector table” table, changed “WKUP” to “WKPU”.
In the “INTC memory map” table, added the module base address.
Memory Protection
Unit
In the “MPU block diagram” figure, changed the text at the top left to “Platform” and removed
“z0hn1 or”.
Revised the Introduction section.
Changed AHB to XBAR.
Deleted references to IPS and replaced with “peripheral” as needed.
In the “MPU access evaluation macro” figure, changed “AHB_ap” to “System bus address
phase”.
In the “MPU memory map” table, added the module base address.
System Integration Unit
Lite
In the MIDR1[PARTNUM] field, removed the “(560x)” text fragments.
Changed “WARNING” to “CAUTION”.
In the register figures, changed “Access: None” to the corresponding actual level of access.
In the MIDR1[PKG] field description:
• Added “Any values not explicitly specified are reserved”.
• Added the 64-pin LQFP setting.
Revised the description of the PARTNUM field in MIDR1 and MIDR2 to clarify that the field
is split between the two registers.
In the PCRx section, revised the WPS and WPE field descriptions to indicate the correct
functionality.
In the “External interrupts” section, changed “This register is a clear-by-write-1 register
type, preventing inadvertent overwriting of other flags in the same register.” to “The bits
in the ISR[EIF] field are cleared by writing a ‘1’ to them; this prevents inadvertent
overwriting of other flags in the register.”
Revised the “MIDR2 field descriptions” table to show how to calculate total flash memory
size.
In the “MIDR2 field descriptions” table, deleted the entry for FR (not implemented).
In the “SIUL memory map” table, added the module base address.
Inter-Integrated Circuit
Bus Controller Module
In the IBCR section, changed “MS/SL
” to “MSSL” and “Tx/Rx” to “TXRX” to ensure
compliance with field name convention.
In the IBCR figure, changed bit 7 (was IBDOZE, is reserved).
In the IBSR figure, changed the IBAL and IBIF fields to w1c.
In the “Interrupt description” section, changed “(TCF bit set - To be checked)” to “(a Byte
Transfer interrupt occurs whenever the TCF bit changes from 0 to 1, that is, Transfer
Under Progress to Transfer Complete state)”.
Revised the last paragraph of the Overview section.
In the IBCR[MDIS] field description, added “Status register bits (IBSR) are not valid when
module is disabled”.
In the IBSR[RXAK] field description, added “This bit is valid only after transfer is complete”.
In the “Interrupt description” section, revised the entry for “Byte transfer condition”.
In the “Initialization sequence” section, changed IBCR[IBDIS] to IBCR[MDIS].
Revised the “Post-transfer software response” section.
Added the “Transmit/receive sequence” section.
In the “Generation of STOP” section, in the code sample, changed “bit 1” to “bit 5”.
In the “I2C memory map” table, added the module base address.
Table B-1. Changes between revisions 7 and 8 (continued)
Chapter Description
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