MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 907
LIN Controller In the “IFER field descriptions” table, switched “activated” and “deactivated” in order to
match with “IFER[FACT] configuration” table.
Deleted the “Register map and reset values” section (duplicate content).
In the “UART mode” section, in the “9-bit frames” subsection, changed “sum of the 7 data
bits” to “sum of the 8 data bits”.
In the LINCR1[BF] field description, changed “this bit is reserved” to “this bit is reserved and
always reads 1”.
Changed “kbps” to “Kbit/s”.
FlexCAN In the “FlexCAN memory map” table, added the module base addresses.
Deserial Serial
Peripheral Interface
In the “Continuous selection format” section, added a note about filling the TX FIFO.
Added new rules to the “Continuous serial communications clock” section.
In the “DSPI memory map” table, added the module base addresses.
Timers Added this chapter (incorporates content from STM, eMIOS, and PIT chapters).
Analog-to-Digital
Converter
Updated MCR[WLSIDE] bit description.
Updated CDR register.
Replaced ADCDig with ADC, rewriting content as necessary.
In the PDEDR[PDED] field description, added “The delay is to allow time for the ADC power
supply to settle before commencing conversions.”.
In the “Threshold registers” Introduction section, deleted the sentence “The inverter bit and
the mask bit for mask the interrupt are stored in the TRC registers.”.
Deleted the “Bit access descriptions” table.
In the CIMR section, deleted the duplicate CIMR1 figure.
Cross Triggering Unit Removed remaining references to CTU_CSR (not implemented on this chip).
In the “CTU memory map” table:
• Changed the end address of the reserved space (was 0x002C, is 0x002F).
• Added the module base address.
Flash Memory Replaced the entire chapter.
Register Protection Added this chapter.
Software Watchdog
Timer
Added this chapter.
Error Correction Status
Module
Revised the Introduction section.
Revised the Features section.
Revised the MUDCR section to show completely that bit 1 is reserved.
In the register descriptions, revised the names as needed to match the names in the
memory map.
In the PREMR section, added text on where to find bus master IDs.
Aligned register names in the descriptions and the memory map.
Deleted the second paragraph in the Introduction section.
Deleted the last bullet (about spp_ips_reg_protection) in the Features section.
In the PREAT field descriptions, changed “AMBA-AHB” to “XBAR”.
Renamed the “Spp_ips_reg_protection” section to “Register protection” and revised the
section.
Revised the “ECC registers” section.
In the “ECSM memory map” table, added the module base address.
IEEE 1149.1 Test
Access Port Controller
In the Features section, changed “Three test data registers” to “2 test data registers”.
In the “SAMPLE instruction” section, added information about pad status.
In the “SAMPLE/PRELOAD instruction” section, added information about pad status.
Table B-1. Changes between revisions 7 and 8 (continued)
Chapter Description
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