MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 81
Figure 5-11. FlexCAN bit timing
5.2.3.2 Protocol
Table 5-9 summarizes the protocol and BAM action during this boot mode. All data are transmitted byte
wise.
Table 5-9. FlexCAN boot mode download protocol
Protoco
l
step
Host sent message
BAM response
message
Action
1 CAN ID 0x011 +
64-bit password
CAN ID 0x001 +
64-bit password
Password checked for validity and compared against stored
password
2 CAN ID 0x012 +
32-bit store
address + VLE
bit + 31-bit number of
bytes
CAN ID 0x002 +
32-bit store
address + VLE
bit + 31-bit number of
bytes
Load address is stored for future use.
Size of download are stored for future use.
Verify if VLE bit is set to 1
3 CAN ID 0x013 +
8 to 64 bits of raw
binary data
CAN ID 0x003 +
8 to 64 bits of raw
binary data
8-bit data are packed into 32-bit words. These words are
saved into SRAM starting from the “Load address”.
“Load address” increments until the number of data
received and stored matches the size as specified in the
previous step.
5 None None Branch to downloaded code
SYNC_SEG Time segment 1 Time segment 2
Sample point
NRZ signal
Transmit point
1
time quantum time quanta time quanta
7 2
1 bit time
1 time quantum = 4 system clock periods
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