MPC5604B/C Microcontroller Reference Manual, Rev. 8
912 Freescale Semiconductor
Clock Description Section 3.5, “Memory Map and Register Definition”, Section 3.5.1, “Register Descriptions”
Added ‘Location’ column to MC_CGM Register Description; added clock domain
information to clock source selection register descriptions
Section 3.6, “Slow internal RC oscillator (SIRC) digital interface”: Replaced all LPRC
occurrences with SIRC
Section 3.8.6.1, “Normal mode”: Replaced “CR“ with “CR.NDIV“ and “LDF” with “NDIV“
Fast External Crystal Oscillator Control Register (FXOSC_CTL) field descriptions: Updated
description of EOCV[7:0]
FMPLL block diagram: Added footnote to DIV2
FMPLL memory map: Updated access types
CR field descriptions: Updated description of field EN_PLL_SW
Progressive clock switching on pll_select rising edge: Updated column header titles
Added figure “FMPLL output clock division flow during progressive switching”
Mode Entry Module added note for S_MTRANS polling; cleaned up MC_ME Mode Diagram; added details to
RESET mode description; added details of booting from backup RAM on STANDBY0 exit
Boot Assist Module Updated oscillator naming
Removed all references to “autobaud” and to ABD field of SSCM_STATUS register
(autobaud feature not supported by device)
Section 8.3.2, “Reset Configuration Half Word Source (RCHW)”: Changed offset from 0x02
to 0x00
Section 8.3.3, “Single chip boot mode”: Added a footnote
BAM memory organization: Added column header “Parameter”
Updated Fields of SSCM STATUS register used by BAM
Section 8.3.4.3, “BAM resources”: Updated list of MCU resources
Section 8.3.4.4, “Download and execute the new code”: Removed optional first step No. 0
(step concerned send/receive message for autobaud rate selection)
Updated Serial boot mode – baud rates
Updated System clock frequency related to external clock frequency
Reset Configuration Half Word (RCHW): Changed reset value for all fields: was 0; is 1
Updated Section 8.3.4.5, “Download 64-bit password and password check”
System Integration Unit
Lite
Updated SIUL signal properties
Updated SIUL memory map
Updated register descriptions
Section 7.6.2, “General purpose input and output pads (GPIO)”: Updated number of
interrupt vectors and number of external interrupts
e200z0h Core Updated e200z0h block diagram
Section 10.2.1.5, “e200z0h system bus features”: Added footnotes
Peripheral Bridge Chapter title change
Replaced “AIPS” with “peripheral bridge”, or “PBRIDGE” where appropriate, throughout
chapter
Peripheral bridge interface: Updated PBRIDGE1 peripheral names
Updated Section 11.1.4, “Modes of operation”
Crossbar Switch Updated XBAR block diagram
Table B-4. Changes between revisions 2 and 4 (continued)
Chapter Description
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