MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 913
Memory Protection
Unit
Updated MPU block diagram
Updated Section 13.5.2, “Register description” to include adding bit numbers to field names
and changing field bit numbers format to LSB=0 where needed
MPU memory map: Removed MPU_EAR3 and MPU_EDR3
MPU Error Address Register, Slave Port n (MPU_EARn): Removed MPU_EAR3 content
MPU Error Detail Register, Slave Port n (MPU_EDRn): Removed MPU_EDR3 content
MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0): Replaced asterisks with
‘0’ as reset value for bits 27:31
MPU_RGDn.Word0 field descriptions: Replaced SRTADDR[31:0] with SRTADDR[26:0]
MPU_RGDn.Word1 field descriptions: Replaced ENDADDR[31:0] with ENDADDR[26:0]
Error Correction Status
Module
Replaced AIPS with “peripheral bridge” or “PBRIDGE”
Section 18.4.2, “Register description”: Applied LSB=0 to field internal bit numbers
ECSM 32-bit memory map: Added ECSM base address
Section 18.4.2.1, “Processor Core Type Register (PCT)”: Added reset values to bitmap
Section 18.4.2.2, “SoC-Defined Platform Revision Register (REV)”: Added reset values to
bitmap
Section 18.4.2.3, “IPS On-Platform Module Configuration Register (IOPMC)”: Added reset
values to bitmap
Section 18.4.2.6, “Miscellaneous User-Defined Control Register (MUDCR)”
– Updated bit numbers and field descriptions
– Updated text following field description table
Section 18.4.2.7.1, “ECC Configuration Register (ECR)”: Removed paragraph about
reporting of single-bit memory corrections
Updated ECC Configuration (ECR) field descriptions
Section 18.4.2.7.3, “ECC Error Generation Register (EEGR)”: Removed paragraph about
enabling of error generation modes
Section 18.4.2.7.3, “ECC Error Generation Register (EEGR)”: Replaced “for the ECC
Configuration Register definition” with “for the ECC Error Generation Register definition” in
sentence above bitmap
Updated ECC Error Generation (EEGR) field descriptions
IEEE 1149.1 Test
Access Port Controller
Section 15.1, “Introduction”: Removed paragraph about IEEE 1149.7
e200z0 OnCE Register Addressing: Replaced ‘Shared Nexus Control Register (SNC)’ with
‘Reserved’ (SNC register not implemented on this device)
Nexus Development
Interface
NDI Implementation Block Diagram: Replaced PPC with CPU
Nexus Debug Interface Registers:
– Added ‘Location’ column as navigational aid
– Removed Client Select Control (CSC) Register (CSC register not implemented on this
device)
– Updated register names
– Removed sentence referencing device MPC5516 from footnote 1
Nexus Device ID (DID) Register bitmap: Changed reset value for field MIC—was 0xE, is
0x20
DID field descriptions: Removed “for STMicroelectronics” from MIC field description
PCR field descriptions: Updated description of MCKO_DIV[2:0] and corrected numbering
for LSB=0 throughout table
Updated Section 16.7.3, “Programmable MCKO Frequency”
Section 16.7.4, “Nexus Messaging”: Removed sentence referencing Client Select Control
Register
Section 16.7.6.1, “EVTI Generated Break Request”: Removed sentence referencing
Shared Nexus Control (SNC) Register (SNC register not implemented on this device)
Table B-4. Changes between revisions 2 and 4 (continued)
Chapter Description
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