Freescale Semiconductor MPC5604B - Page 932

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 921
System Integration Unit
Lite
- Repleced the number of I/O pins from “121“ to “123“ for 144-pin and 208-pin packages.
- Repleced the number of I/O pins from “77“ to “79“ for 100-pin packages.
- Ta bl e 7 7: modified the reset value for bit 28:31 to “0“.
- Ta bl e 8 3: changed the size of the field “SRC“ form 2 to 1 bit.
- Ta bl e 8 6: Changed the definition of PCRx.SRC.
Power Control Unit Replaced the entire chapter.
e200z0h Core Replaced all e200z0 e200z1 occurrences with e200z0h.
Error Correction Status
Module
- removed MRSR register and descibed as reserved.
- removed section “13.4.3 High Priority Enables“.
Table 179: removed MRSR register and descibed as reserved.
Section 15.6, “External Signal Description”:
- Updated the period since all 4 JTAG pin are shared with GPIO.
- Ta bl e 1 49: updated DC field description.
- Section 15.8.4, “JTAGC Instructions”: Removed Cut.1 information.
Nexus Development
Interface
- Removed references to JCOMP.
- Removed section “Nexus Reset Control“.
Static RAM - Updated the size of the RAM from 38 to 42KB.
- Section 20.6, “Initialization and application information”: Reformatted.
Flash Memory - Ta bl e 1 68 Updated.
- Section 18.4.1, “Introduction”: Replaced “SPP” with “RPP”.
- Removed figure”FLASH Memory Controller Block Diagram”.
- Ta bl e 2 29: Replaced the reset value with which ones defined in the table footnote and
removed them.
Deserial Serial
Peripheral Interface
- Removed all the note that refer to Rx Mask.
- Removed DSPIx_CTAR6 and DSPIx_CTAR7 register.
- Added following tables: Table 244, Table 245, Ta bl e 24 6, Tabl e 247, Table 248, Table 249,
Table 250, Ta ble 2 51, Table 252, Ta bl e 2 53, Table 254, Table 2 55, Table 2 56 .
Section 19.2, “Features”: Replaced “Eight clock and transfer attribute registers“ with “Six
clock and transfer attribute registers“.
Section 19.5.2, “DSPI Module Configuration Register (DSPIx_MCR)”: Removed CLR_TXF
and CLR_RXF fields from DSPIx_MCR register.
LIN Controller Replaced the entire chapter.
FlexCAN - Removed “[Ref.1]”.
- Section 21.1.2, “FlexCAN module features”.
- Added bullet “Hardware cancellation on Tx message buffers.“ .
- Removed note.
- Ta bl e 3 28: Replaced the footnote with new one.
- Section 21.3.3, “Rx FIFO structure”: Table 282 fixed the offset value.
- Updated Section 21.3.4.1, “Module Configuration Register (MCR)” (MAXMB note).
- Updated Section 21.3.4.8, “Error and Status Register (ESR)” (bit numbers in first
paragraph).
- Fixed information about the number of frames accumulated in the FIFO to generate a
warning interrupt, which is 5. (Affected sections: Section 21.3.4.12, “Interrupt Flags 1
Register (IFLAG1)” and Section 21.4.8, “Rx FIFO”).
- Section 21.4.2, “Local priority transmission”: added.
Table B-5. Changes between revisions 1 and 2 (continued)
Chapter Description