Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-28
In this example, a loop that executes 100 times assigns x to every
even-numbered element and
y to every odd-numbered element. By
unrolling the loop you can make both assignments each iteration,
removing one branch in the loop body.
Compiler Support for Branch Prediction
Compilers can generate code that improves the efficiency of branch
prediction in the Pentium 4 and Pentium M processors. The Intel C++
Compiler accomplishes this by:
• keeping code and data on separate pages
• using conditional move instructions to eliminate branches
• generating code that is consistent with the static branch prediction
algorithm
• inlining where appropriate
• unrolling, if the number of iterations is predictable
With profile-guided optimization, the Intel compiler can lay out basic
blocks to eliminate branches for the most frequently executed paths of a
function or at least improve their predictability. Branch prediction need
not be a concern at the source level. For more information, see the
Intel® C++ Compiler User’s Guide.
Example 2-10 Loop Unrolling
Before unrolling:
do i=1,100
if (i mod 2 == 0) then a(i) = x
else a(i) = y
enddo
After unrolling
do i=1,100,2
a(i) = y
a(i+1) = x
enddo

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)