Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-6
Data Alignment
Make sure that 64-bit SIMD integer data is 8-byte aligned and that
128-bit SIMD integer data is 16-byte aligned. Referencing unaligned
64-bit SIMD integer data can incur a performance penalty due to
accesses that span 2 cache lines. Referencing unaligned 128-bit SIMD
integer data will result in an exception unless the
movdqu (move
double-quadword unaligned) instruction is used. Using the
movdqu
instruction on unaligned data can result in lower performance than using
16-byte aligned references.
Refer to “Stack and Data Alignment” in Chapter 3 for more
information.
Data Movement Coding Techniques
In general, better performance can be achieved if the data is
pre-arranged for SIMD computation (see “Improving Memory
Utilization” in Chapter 3). However, this may not always be possible.
This section covers techniques for gathering and re-arranging data for
more efficient SIMD computation.
Unsigned Unpack
The MMX technology provides several instructions that are used to
pack and unpack data in the MMX registers. The unpack instructions
can be used to zero-extend an unsigned number. Example 4-2 assumes
the source is a packed-word (16-bit) data type.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)