Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
5-26
SSE3 and Horizontal Computation
Sometimes the AOS type of data organization are more natural in
many algebraic formula. SSE3 enhances the flexibility of SIMD
programming for applications that rely on the horizontal computation
model. SSE3 offers several instructions that are capable of horizontal
arithmetic operations.
Example 5-13 demonstrates using SSE3 instructions to calculate dot
products from vectors stored as AOS. The use of HADDPS adds
more flexibility to sue SIMD instructions and eliminated the need to
insert data swizzling and deswizzling code sequences.
Example 5-13 Calculating Dot Products from AOS
a)An example that computes the dot product of two vectors
movaps xmm0, Vector1 ; the destination has a3, a2, a1, a0
movaps xmm1, Vector2 ; the destination has b3, b2, b1, b0
mulps xmm0, xmm1 ; the destination has a3b3, a2b2,
; a1b1, a0b0
haddps xmm0, xmm0 ; the destination has a3b3+a2b2,
; a1b1+a0b0,a3b3+a2b2,a1b1+a0b0
haddps xmm0, xmm0 ; the destination has 4 copies of
; a3b3+a2b2+a1b1+a0b0
(b) An example that computes two dot products from two pair
of vectors.
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)