Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-38
Microarchitecture Pipeline and Hyper-Threading Technology
This section describes the HT Technology microarchitecture and how
instructions from the two logical processors are handled between the
front end and the back end of the pipeline.
Although instructions originating from two programs or two threads
execute simultaneously and not necessarily in program order in the
execution core and memory hierarchy, the front end and back end
contain several selection points to select between instructions from the
two logical processors. All selection points alternate between the two
logical processors unless one logical processor cannot make use of a
pipeline stage. In this case, the other logical processor has full use of
every cycle of the pipeline stage. Reasons why a logical processor may
not use a pipeline stage include cache misses, branch mispredictions,
and instruction dependencies.
Front End Pipeline
The execution trace cache is shared between two logical processors.
Execution trace cache access is arbitrated by the two logical processors
every clock. If a cache line is fetched for one logical processor in one
clock cycle, the next clock cycle a line would be fetched for the other
logical processor provided that both logical processors are requesting
access to the trace cache.
If one logical processor is stalled or is unable to use the execution trace
cache, the other logical processor can use the full bandwidth of the trace
cache until the initial logical processor’s instruction fetches return from
the L2 cache.
After fetching the instructions and building traces of µops, the µops are
placed in a queue. This queue decouples the execution trace cache from
the register rename pipeline stage. As described earlier, if both logical
processors are active, the queue is partitioned so that both logical
processors can make independent forward progress.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)