Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-7
• Avoid longer latency instructions: integer multiplies and divides.
Replace them with alternate code sequences (e.g., use shifts instead
of multiplies).
• Use the lea instruction and the full range of addressing modes to do
address calculation.
• Some types of stores use more µops than others, try to use simpler
store variants and/or reduce the number of stores.
• Avoid use of complex instructions that require more than 4 µops.
• Avoid instructions that unnecessarily introduce dependence-related
stalls:
inc and dec instructions, partial register operations (8/16-bit
operands).
• Avoid use of ah, bh, and other higher 8-bits of the 16-bit registers,
because accessing them requires a shift operation internally.
• Use xor and pxor instructions to clear registers and break
dependencies for integer operations; also use
xorps and xorpd to
clear XMM registers for floating-point operations.
• Use efficient approaches for performing comparisons.
Optimize Instruction Scheduling
• Consider latencies and resource constraints.
• Calculate store addresses as early as possible.
Enable Vectorization
• Use the smallest possible data type. This enables more parallelism
with the use of a longer vector.
• Arrange the nesting of loops so the innermost nesting level is free of
inter-iteration dependencies. It is especially important to avoid the
case where the store of data in an earlier iteration happens lexically
after the load of that data in a future iteration (called
lexically-backward dependence).

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)