Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-18
Table B-1 Pentium 4 Processor Performance Metrics
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required
General Metrics
Non-Sleep
Clockticks
The number of
clockticks.while a
processor is not in
any sleep modes.
See explanation on how
to count clocks in section
“Counting Clocks”.
Non-Halted
Clockticks
The number of
clockticks that the
processor is in not
halted nor in sleep.
Global_power_events RUNNING
Instructions
Retired
Non-bogus IA-32
instructions executed
to completion. May
count more than
once for some
instructions with
complex uop flow
and were interrupted
before retirement.
The count may vary
depending on the
microarchitectural
states when counting
begins.
Instr_retired NBOGUSNTAG|
NBOGUSTAG
Non-Sleep CPI Cycles per
instruction for a
physical processor
package.
(Non-Sleep Clockticks) /
(Instructions Retired)
Non-Halted CPI Cycles per
instruction for a
logical processor.
(Non-Halted Clockticks) /
(Instructions Retired)
μops Retired Non-bogus μops
executed to
completion
uops_retired NBOGUS
UPC μop per cycle for a
logical processor
μops Retired/ Non-Halted
Clockticks
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)