Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-34
Software Prefetch and Cache Blocking Techniques
Cache blocking techniques, such as strip-mining, are used to improve
temporal locality, and thereby cache hit rate. Strip-mining is a
one-dimensional temporal locality optimization for memory. When
two-dimensional arrays are used in programs, loop blocking technique
(similar to strip-mining but in two dimensions) can be applied for a
better memory performance.
If an application uses a large data set that can be reused across multiple
passes of a loop, it will benefit from strip mining: data sets larger than
the cache will be processed in groups small enough to fit into cache.
This allows temporal data to reside in the cache longer, reducing bus
traffic.
Data set size and temporal locality (data characteristics) fundamentally
affect how prefetch instructions are applied to strip-mined code.
Figure 6-6 shows two simplified scenarios for temporally-adjacent data
and temporally-non-adjacent data.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)