Intel ARCHITECTURE IA-32 User Manual

Application Performance Tools A
A-5
Vectorizer Switch Options
The Intel C++ and Fortran Compiler can vectorize your code using the
vectorizer switch options. The options that enable the vectorizer are
the
-Qx[M,K,W,B,P] and -Qax[M,K,W,B,P] described above. The
compiler provides a number of other vectorizer switch options that
allow you to control vectorization. The latter switches require the
-Qx[M,K,W,B,P] or -Qax[M,K,W,B,P] switch to be on. The default is
off.
In addition to the
-Qx[M,K,W,B,P] or -Qax[M,K,W,B,P] switches, the
compiler provides the following vectorization control switch options:
-Qvec_report[n] Controls the vectorizer’s diagnostic levels,
where n is either 0, 1, 2, or 3.
-Qrestrict Enables pointer disambiguation with the
restrict qualifier.
Loop Unrolling
The compilers automatically unroll loops with the -Qx[M,K,W,B,P] and
-Qax[M,K,W,B,P] switches.
To disable loop unrolling, specify -
Qunroll0.
CAUTION. When you use -Qax[extensions] in
conjunction with
-Qx[extensions], the extensions
specified by
-Qx[extensions] can be used
unconditionally by the compiler, and the resulting
program will require the processor extensions to
execute properly.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)