Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-51
The performance metrics listed in Table B-1 fall into three categories:
• Logical processor specific and supporting parallel counting.
• Logical processor specific but constrained by ESCR limitations.
• Logical processor independent and not supporting parallel counting.
Table B-5 lists performance metrics in the first and second category.
Table B-6 lists performance metrics in the third category.
There are four specific performance metrics related to the trace cache
that are exceptions to the three categories above. They are:
• Logical Processor 0 Deliver Mode
• Logical Processor 1 Deliver Mode
• Logical Processor 0 Build Mode
• Logical Processor 0 Build Mode
Each of these four metrics cannot be qualified by programming bit 0 to
4 in the respective ESCR. However, it is possible and useful to collect
two of these four metrics simultaneously.
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting
General Metrics Uops Retired
Instructions Retired
Instructions Completed
Speculative Instructions Completed
Non-Halted Clockticks
Speculative Uops Retired
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)