Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Floating-point Applications 5
5-23
SSE3 and Complex Arithmetics
The flexibility of SSE3 in dealing with AOS-type of data structure can
be demonstrated by the example of multiplication and division of
complex numbers. For example, a complex number can be stored in a
structure consisting of its real and imaginary part. This naturally leads to
the use of an array of structure. Example 5-11 demonstrates using SSE3
Figure 5-4 Asymmetric Arithmetic Operation of the SSE3 Instruction
Figure 5-5 Horizontal Arithmetic Operation of the SSE3 Instruction HADDPD
X1 X0
X1 + Y1 X0 -Y0
SUB
Y1 Y0
ADD
X1 X0
Y0 + Y1 X0 + X1
ADD
Y1 Y0
ADD

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)