Intel ARCHITECTURE IA-32 User Manual

Multi-Core and Hyper-Threading Technology 7
7-3
Figure 7-1 illustrates how performance gains can be realized for any
workload according to Amdahl’s law. The bar in Figure 7-1 represents
an individual task unit or the collective workload of an entire
application.
In general, the speed-up of running multiple threads on an MP systems
with N physical processors, over single-threaded execution, can be
expressed as:
where P is the fraction of workload that can be parallelized, and O
represents the overhead of multithreading and may vary between
different operating systems. In this case, performance gain is the inverse
of the relative response.
Figure 7-1 Amdahl’s Law and MP Speed-up
RelativeResponse
Tsequential
Tparallel
-------------------------------= 1 P–
P
N
---- O++
⎝⎠
⎛⎞
=
1-P
P
Tsequential
1-P
P/2
Tparallel
P/2
Single Thread
Multi-Thread on MP
Overhead

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)