Intel ARCHITECTURE IA-32 User Manual

Multi-Core and Hyper-Threading Technology 7
7-19
• For each processor supporting Hyper-Threading Technology,
consider adding functionally uncorrelated threads to increase the
hardware resource utilization of each physical processor package.
See “Using Thread Affinities to Manage Shared Platform Resources”
for more details.
Generality and Performance Impact
The next five sections cover the optimization techniques in detail.
Recommendations discussed in each section are ranked by importance
in terms of estimated local impact and generality.
Rankings are subjective and approximate. They can vary depending on
coding style, application and threading domain. The purpose of
including high, medium and low impact ranking with each
recommendation is to provide a relative indicator as to the degree of
performance gain that can be expected when a recommendation is
implemented.
It is not possible to predict the likelihood of a code instance across many
applications, so an impact ranking cannot be directly correlated to
application-level performance gain. The ranking on generality is also
subjective and approximate.
Coding recommendations that do not impact all three scaling factors are
typically categorized as medium or lower.
Thread Synchronization
Applications with multiple threads use synchronization techniques in
order to ensure correct operation. However, thread synchronization that
are improperly implemented can significantly reduce performance.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)