Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-50
Table B-5 New Metrics for Pentium 4 Processor (Family 15, Model 3)
Using Performance Metrics with Hyper-Threading
Technology
On Intel Xeon processors that support Hyper-Threading Technology, the
performance metrics listed in Table B-1 may be qualified to associate
the counts with a specific logical processor, provided the relevant
performance monitoring events supports qualification by logical
processor. Within the subset of those performance metrics that support
qualification by logical processors, some of them can be programmed
with parallel ESCRs and CCCRs to collect separate counts for each
logical processor simultaneously. For some metrics, qualification by
logical processor is supported but there is not sufficient number of
MSRs for simultaneous counting of the same metric on both logical
processors. In both cases, it is also possible to program the relevant
ESCR for a performance metric that supports qualification by logical
processor to produce counts that are, typically, the sum of contributions
from both logical processors.
A number of performance metrics are based on performance monitoring
events that do not support qualification by logical processor. Any
attempts to program the relevant ESCRs to qualify counts by logical
processor will not produce different results. The results obtained in this
manner should not be summed together.
Metric Descriptions
Event Name or
Metric Expression
Event Mask value
required
Instructions
Completed
Non-bogus IA-32
instructions
completed and
retired.
instr_completed
NBOGUS
Speculative
Instructions
Completed
Number of IA-32
instructions decoded
and executed
speculatively.
instr_completed
BOGUS

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)