Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-15
If all of the operands in a register are being replaced by a series of
pinsrw instructions, it can be useful to clear the content and break the
dependence chain by either using the
pxor instruction or loading the
register. See the “Clearing Registers” section in Chapter 2.
Figure 4-6 pinsrw Instruction
Example 4-8 pinsrw Instruction Code
; Input:
; edx pointer to source value
; Output:
; mm0 register with new 16-bit value inserted
;
mov eax, [edx]
pinsrw mm0, eax, 1
OM15164
Y2
MM
R32
31 0
31 063
X4 X3 Y1 X1
Y1

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)