Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-73
Note that transcendental functions are supported only in x87 floating
point, not in Streaming SIMD Extensions or Streaming SIMD
Extensions 2.
Instruction Selection
This section explains how to generate optimal assembly code. The listed
optimizations have been shown to contribute to the overall performance
at the application level on the order of 5%. Performance gain for
individual applications may vary.
The recommendations are prioritized as follows:
• Choose instructions with shorter latencies and fewer µops.
• Use optimized sequences for clearing and comparing registers.
• Enhance register availability.
• Avoid prefixes, especially more than one prefix.
Assembly/Compiler Coding Rule 37. (M impact, H generality) Choose
instructions with shorter latencies and fewer micro-ops. Favor
single-micro-operation instructions.
A compiler may be already doing a good job on instruction selection as
it is. In that case, user intervention usually is not necessary.
Assembly/Compiler Coding Rule 38. (M impact, L generality) Avoid
prefixes, especially multiple non-0F-prefixed opcodes.
Assembly/Compiler Coding Rule 39. (M impact, L generality) Do not use
many segment registers.
On the Pentium M processor, there is only one level of renaming of
segment registers.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)