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Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
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General Optimization Guidelines 2
2-81
Processing an instruction with the 0x66 prefix that (i) has a modr/m
byte in its encoding and (ii) the opcode byte of the instruction
happens to be aligned on byte 14 of an instruction fetch line. The
performance delay in this case is approximately twice of those other
two situations.
Assembly/Compiler Coding Rule 49. (ML impact, M generality) Avoid
using a length changing prefix on instructions with immediate values. The most
common scenario for this is using an 0x66 prefix for 16-bit immediate in 32-bit
code. Also avoid using the 0x66 prefix in conjunction with the 0xF7 opcode
group of instructions.
Assembly/Compiler Coding Rule 50. (ML impact, L generality) When there
is a need to use 0x66 prefix in an instruction requiring a modr/m byte, consider
adjusting code alignment by adding a nop before the instruction to avoid the
opcode byte aligning on byte 14 from the beginning of an instruction fetch line.
REP Prefix and Data Movement
The REP prefix is commonly used with string move instructions for
memory related library functions such as memcpy (using rep movsd) or
memset (using rep stos). These string/mov instructions with the REP
prefixes are implemented in MS-ROM and have several implementation
variants with different performance levels.
The specific variant of the implementation is chosen at execution time
based on data layout, alignment and the counter (ecx) value. For
example, movsb/stosb with REP prefix should be used with counter
value less or equal than three for best performance.
Table 2-4 Avoiding False LCP Delays with 0xF7 Group Instructions
A Sequence Causing Delay
in the Decoder Alternate Sequence to Avoid Delay
neg word ptr a
movsx eax,word ptr a
neg eax
mov word ptr a,ax

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Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

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