Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
9-2
Pentium M, Intel Core Solo and Intel Core Duo processors implement
features designed to enable the reduction of active power and static
power consumption. These include:
• Enhanced Intel SpeedStep
®
Technology enables operating system
(OS) to program a processor to transition to lower frequency and/or
voltage levels while executing a workload.
• Support for various activity states (for example: Sleep states, ACPI
C-states) to reduces static power consumption by turning off power
to sub-systems in the processor.
Enhanced Intel SpeedStep Technology provides low-latency transitions
between operating points that support P-state usages. In general, a
high-numbered P-state operates at a lower frequency to reduce active
power consumption. High-numbered C-state types correspond to more
aggressive static power reduction. The trade-off is that transitions out of
higher-numbered C-states have longer latency.
Mobile Usage Scenarios
In mobile usage models, heavy loads occur in bursts while working on
battery power. Most productivity, web, and streaming workloads require
modest performance investments. Enhanced Intel SpeedStep
Technology provides an opportunity for an OS to implement policies
that track the level of performance history and adapt the processor’s
frequency and voltage. If demand changes in the last 300 ms
3
, the
technology allows the OS to optimize the target P-state by selecting the
lowest possible frequency to meet demand.
Consider, for example, an application that changes processor utilization
from 100% to a lower utilization and then jumps back to 100%. The
diagram in Figure 9-1 shows how the OS changes processor frequency
3. This chapter uses several numerical values of various time constants (300 ms, 100 ms, etc)
on power management decisions as examples to illustrate the order of magnitude or relative
magnitude. Actual values used in OSes will vary by vendor and/or may vary between
product releases from the same vendor.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)