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Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
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Coding for SIMD Architectures 3
3-17
The intrinsic data types, however, are not a basic ANSI C data type, and
therefore you must observe the following usage restrictions:
Use intrinsic data types only on the left-hand side of an assignment
as a return value or as a parameter. You cannot use it with other
arithmetic expressions (for example, “
+”, “>>”).
Use intrinsic data type objects in aggregates, such as unions to
access the byte elements and structures; the address of an
__m64
object may be also used.
Use intrinsic data type data only with the MMX technology
intrinsics described in this guide
.
For complete details of the hardware instructions, see the Intel
Architecture MMX Technology Programmers Reference Manual. For
descriptions of data types, see the IA-32 Intel® Architecture Software
Developers Manual, Volumes 2A & 2B.
Classes
A set of C++ classes has been defined and available in Intel C++
Compiler to provide both a higher-level abstraction and more flexibility
for programming with MMX technology, Streaming SIMD Extensions
and Streaming SIMD Extensions 2. These classes provide an
easy-to-use and flexible interface to the intrinsic functions, allowing
developers to write more natural C++ code without worrying about
which intrinsic or assembly language instruction to use for a given
operation. Since the intrinsic functions underlie the implementation of
these C++ classes, the performance of applications using this
methodology can approach that of one using the intrinsics. Further
details on the use of these classes can be found in the Intel C++ Class
Libraries for SIMD Operations Users Guide, order number 693500.
Example 3-11 shows the C++ code using a vector class library. The
example assumes the arrays passed to the routine are already aligned to
16-byte boundaries.

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Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

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