Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-8
Intel NetBurst
®
Microarchitecture
The Pentium 4 processor, Pentium 4 processor Extreme Edition
supporting Hyper-Threading Technology, Pentium D processor,
Pentium processor Extreme Edition and the Intel Xeon processor
implement the Intel NetBurst microarchitecture.
This section describes the features of the Intel NetBurst
microarchitecture and its operation common to the above processors. It
provides the technical background required to understand optimization
recommendations and the coding rules discussed in the rest of this
manual. For implementation details, including instruction latencies, see
Appendix C, “IA-32 Instruction Latency and Throughput.”
Intel NetBurst microarchitecture is designed to achieve high
performance for integer and floating-point computations at high clock
rates. It supports the following features:
• hyper-pipelined technology that enables high clock rates
• a high-performance, quad-pumped bus interface to the Intel
NetBurst microarchitecture system bus
• a rapid execution engine to reduce the latency of basic integer
instructions
• out-of-order speculative execution to enable parallelism
• superscalar issue to enable parallelism
• hardware register renaming to avoid register name space limitations
• cache line sizes of 64 bytes
• hardware prefetch
Design Goals of Intel NetBurst Microarchitecture
The design goals of Intel NetBurst microarchitecture are:
• to execute legacy IA-32 applications and applications based on
single-instruction, multiple-data (SIMD) technology at high
throughput

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)