Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
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Eliminate 64-KByte Aliased Data Accesses
The 64 KB aliasing condition is discussed in Chapter 2. Memory
accesses that satisfy the 64 KB aliasing condition can cause excessive
evictions of the first-level data cache. Eliminating 64-KB-aliased data
accesses originating from each thread helps improve frequency scaling
in general. Furthermore, it enables the first-level data cache to perform
efficiently when Hyper-Threading Technology is fully utilized by
software applications.
User/Source Coding Rule 34. (H impact, H generality) Minimize data
access patterns that are offset by multiples of 64 KB in each thread.
The presence of 64-KB-aliased data access can be detected using
Pentium 4 processor performance monitoring events. Appendix B
includes an updated list of Pentium 4 processor performance metrics.
These metrics are based on events accessed using the Intel VTune
performance analyzer.
Performance penalties associated with 64 KB aliasing are applicable
mainly to current processor implementations of Hyper-Threading
Technology or Intel NetBurst microarchitecture. The next section
discusses memory optimization techniques that are applicable to
multithreaded applications running on processors supporting
Hyper-Threading Technology.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)