Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-19
Static Prediction
Branches that do not have a history in the BTB (see the “Branch
Prediction” section) are predicted using a static prediction algorithm.
The Pentium 4, Pentium M, Intel Core Solo and Intel Core Duo
processors have similar static prediction algorithms:
• Predict unconditional branches to be taken.
• Predict indirect branches to be NOT taken.
In addition, conditional branches in processors based on the Intel
NetBurst microarchitecture are predicted using the following static
prediction algorithm:
• Predict backward conditional branches to be taken. This rule is
suitable for loops.
• Predict forward conditional branches to be NOT taken.
Pentium M, Intel Core Solo and Intel Core Duo processors do not
statically predict conditional branches according to the jump direction.
All conditional branches are dynamically predicted, even at their first
appearance.
Example 2-4 Use of pause Instruction
lock: cmp eax, A
jne loop
; code in critical section:
loop: pause
cmp eax, A
jne loop
jmp lock

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)